"A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a ..."

John Barth et al. (2007)

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DOI: 10.1109/ISSCC.2007.373506

access: closed

type: Conference or Workshop Paper

metadata version: 2022-03-02

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John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC 2007: 486-617

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