"A High Speed VLSI Implementation of 256-bit Scalar Point Multiplier for ..."

Jianwei Liu et al. (2018)

> Home

Details and statistics

DOI: 10.1109/IISR.2018.8535680

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isr2/LiuGCW18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isr2/LiuGCW18
Jianwei Liu, Zhenyu Guan, Dongxu Cheng, Ziyu Wang:
A High Speed VLSI Implementation of 256-bit Scalar Point Multiplier for ECC over GF (p). ISR 2018: 184-191

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.