Stop the war!
Остановите войну!
for scientists:
default search action
"Process Variation Aware Timing Optimization through Transistor Sizing in ..."
Kumar Yelamarthi, Chien-In Henry Chen (2008)
- Kumar Yelamarthi, Chien-In Henry Chen:
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ISQED 2008: 143-147
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.