"Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with ..."

Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang (2019)

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DOI: 10.1109/ISQED.2019.8697706

access: closed

type: Conference or Workshop Paper

metadata version: 2019-05-04

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Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang:
Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. ISQED 2019: 231-234

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