"An automated design methodology for yield aware analog circuit synthesis ..."

Sabyasachi Deyati, Pradip Mandal (2011)

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DOI: 10.1109/ISQED.2011.5770730

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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Sabyasachi Deyati, Pradip Mandal:
An automated design methodology for yield aware analog circuit synthesis in submicron technology. ISQED 2011: 229-235

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