"Transistor level placement for full custom datapath cell design."

Durgam Vahia, Maciej J. Ciesielski (1999)

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DOI: 10.1145/299996.300049

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Durgam Vahia, Maciej J. Ciesielski:
Transistor level placement for full custom datapath cell design. ISPD 1999: 158-163

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