"Optimal partitioned fault-tolerant bus layout for reducing power in ..."

Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen (2006)

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DOI: 10.1145/1123008.1123030

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen:
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. ISPD 2006: 114-119

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