"Integrated floorplanning with buffer/channel insertion for bus-based ..."

Faran Rafiq et al. (2002)

> Home

Details and statistics

DOI: 10.1145/505388.505403

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ispd/RafiqCYS02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ispd/RafiqCYS02
Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ISPD 2002: 56-61

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.