"A Scan-Based Lower-Power Testing Architecture for Modern Circuits."

Jiann-Chyi Rau, Jia-Xiang Wang (2021)

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DOI: 10.1109/ISPACS51563.2021.9651069

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-09

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Jiann-Chyi Rau, Jia-Xiang Wang:
A Scan-Based Lower-Power Testing Architecture for Modern Circuits. ISPACS 2021: 1-2

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