"Design of timing-error-resilient systolic arrays for matrix multiplication."

Hsin-Chou Chi, Hsi-Che Tseng, Kun-Lin Tsai (2011)

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DOI: 10.1109/ISOCC.2011.6138749

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Hsin-Chou Chi, Hsi-Che Tseng, Kun-Lin Tsai:
Design of timing-error-resilient systolic arrays for matrix multiplication. ISOCC 2011: 219-222

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