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"Design Methodologies for Ternary Logic Circuits."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Chetan Vudadha, M. B. Srinivas (2018)

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DOI: 10.1109/ISMVL.2018.00041

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Chetan Vudadha, M. B. Srinivas:
Design Methodologies for Ternary Logic Circuits. ISMVL 2018: 192-197

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last updated on 2023-03-23 23:59 CET by the dblp team

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