"Parallel Hardware Algorithms with Redundant Number Representations for ..."

Shoji Kawahito et al. (1992)

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DOI: 10.1109/ISMVL.1992.186815

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Shoji Kawahito, Y. Mitsui, Makoto Ishida, Tetsuro Nakamura:
Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI. ISMVL 1992: 337-345

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