"Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based ..."

Takashi Hirayama et al. (2023)

> Home

Details and statistics

DOI: 10.1109/ISMVL57333.2023.00038

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-28

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ismvl/HirayamaSYN23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ismvl/HirayamaSYN23
Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani:
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. ISMVL 2023: 153-157

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.