"Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing."

Gerhard W. Dueck et al. (1992)

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DOI: 10.1109/ISMVL.1992.186779

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/ismvl/DueckETB92
Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler:
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74

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