"A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude ..."

Shusuke Yoshimoto et al. (2012)

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DOI: 10.1145/2333660.2333683

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-11

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Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90

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