"0.5-V operation variation-aware word-enhancing cache architecture using ..."

Yohei Nakata et al. (2010)

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DOI: 10.1145/1840845.1840888

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-11

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  - conf/islped/NakataOKY10
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Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED 2010: 219-224

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