"Low-power VLSI decoder architectures for LDPC codes."

Mohammad M. Mansour, Naresh R. Shanbhag (2002)

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DOI: 10.1145/566408.566483

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Mohammad M. Mansour, Naresh R. Shanbhag:
Low-power VLSI decoder architectures for LDPC codes. ISLPED 2002: 284-289

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