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"Transistor-level monolithic 3D standard cell layout optimization for ..."
Bon Woong Ku et al. (2017)
- Bon Woong Ku, Taigon Song, Arthur Nieuwoudt, Sung Kyu Lim:
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity. ISLPED 2017: 1-6
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