"Retiming-based logic synthesis for low-power."

Yu-Lung Hsu, Sying-Jyan Wang (2002)

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DOI: 10.1145/566408.566480

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/islped/HsuW02
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Yu-Lung Hsu, Sying-Jyan Wang:
Retiming-based logic synthesis for low-power. ISLPED 2002: 275-278

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