"Processor caches with multi-level spin-transfer torque ram cells."

Yiran Chen et al. (2011)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-04

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  dblp key:
  - conf/islped/ChenWLK11
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  persistent URL:
  - https://dblp.org/rec/conf/islped/ChenWLK11
Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh:
Processor caches with multi-level spin-transfer torque ram cells. ISLPED 2011: 73-78

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