![](https://dblp.uni-trier.de./img/logo.320x120.png)
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
"Transistor sizing for minimizing power consumption of CMOS circuits under ..."
Manjit Borah, Robert Michael Owens, Mary Jane Irwin (1995)
- Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. ISLPD 1995: 167-172
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.