"Feasibility of Parasitic Drain Inductance Design for Minimizing Switching ..."

Koki Abe et al. (2021)

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DOI: 10.1109/ISIE45552.2021.9576373

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Koki Abe, Masataka Ishihara, Yusuke Hatakenaka, Kazuhiro Umetani, Eiji Hiraki:
Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs. ISIE 2021: 1-5

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