"An Efficient Design Methodology for CNFET Based Ternary Logic Circuits."

Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas (2016)

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DOI: 10.1109/INIS.2016.070

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-08

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Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas:
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. iNIS 2016: 278-283

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