"Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA."

B. S. Chandrasekhar, S. Deepanjali, Sk. Noor Mahammad (2022)

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DOI: 10.1109/ISES54909.2022.00018

access: closed

type: Conference or Workshop Paper

metadata version: 2023-02-15

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B. S. Chandrasekhar, S. Deepanjali, Sk. Noor Mahammad:
Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA. iSES 2022: 31-35

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