"Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs."

Surajit Kumar Roy et al. (2011)

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DOI: 10.1109/ISED.2011.29

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman:
Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. ISED 2011: 230-235

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