"A New Design of an N-Bit Reversible Arithmetic Logic Unit."

Subhankar Pal et al. (2014)

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DOI: 10.1109/ISED.2014.56

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-08

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Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika:
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED 2014: 224-225

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