"Design and Analysis of a Robust, High Speed, Energy Efficient 18 ..."

Subhramita Basak et al. (2012)

> Home

Details and statistics

DOI: 10.1109/ISED.2012.23

access: closed

type: Conference or Workshop Paper

metadata version: 2019-05-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ised/BasakSMCS12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ised/BasakSMCS12
Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar:
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. ISED 2012: 130-134

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.