"Design of low-power and high-performance 10 nm SRAM using ..."

Niraj Kumar Singh et al. (2023)

> Home

Details and statistics

DOI: 10.1109/ISDCS58735.2023.10153525

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isdcs/SinghSVS23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isdcs/SinghSVS23
Niraj Kumar Singh, Ravi Shankar, Suraj Verma, Manodipan Sahoo:
Design of low-power and high-performance 10 nm SRAM using Electrostatically doped TMD TFET. ISDCS 2023: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.