"An Efficient Heuristic for Minimizing Maximum Lateness on Parallel Batch ..."

Tsung-Che Chiang, Hsueh-Chien Cheng, Li-Chen Fu (2008)

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DOI: 10.1109/ISDA.2008.73

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/isda/ChiangCF08
Tsung-Che Chiang, Hsueh-Chien Cheng, Li-Chen Fu:
An Efficient Heuristic for Minimizing Maximum Lateness on Parallel Batch Machines. ISDA (2) 2008: 621-627

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