"A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation ..."

Dajiang Zhou, Peilin Liu (2007)

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DOI: 10.1109/ISCAS.2007.377858

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Dajiang Zhou, Peilin Liu:
A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. ISCAS 2007: 2910-2913

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