"Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a ..."

Tong Zhang et al. (2024)

> Home

Details and statistics

DOI: 10.1109/ISCAS58744.2024.10557912

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-08

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/ZhangZJMW24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/ZhangZJMW24
Tong Zhang, Dingguo Zhang, Jing Jin, Patrick P. Mercier, Hui Wang:
Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor. ISCAS 2024: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.