"A two-stage variation-aware task mapping scheme for fault-tolerant ..."

Lei Zhang et al. (2017)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2017.8050632

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/ZhangYXMC17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/ZhangYXMC17
Lei Zhang, Jianxun Yang, Chengbo Xue, Yue Ma, Shan Cao:
A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips. ISCAS 2017: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.