"Multilevel timing-constrained full-chip routing in hierarchical quad-grid ..."

Jin-Tai Yan et al. (2006)

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DOI: 10.1109/ISCAS.2006.1693864

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - conf/iscas/YanCLH06
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Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang:
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. ISCAS 2006

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