"High Throughput/Gate FN-Based Hardware Architectures for AES-OTR."

Rei Ueno et al. (2019)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2019.8702231

access: closed

type: Conference or Workshop Paper

metadata version: 2019-07-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/UenoHIM19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/UenoHIM19
Rei Ueno, Naofumi Homma, Tomonori Iida, Kazuhiko Minematsu:
High Throughput/Gate FN-Based Hardware Architectures for AES-OTR. ISCAS 2019: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.