"VLSI decoding architecture with improved convergence speed and reduced ..."

Yeong-Luh Ueng et al. (2008)

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DOI: 10.1109/ISCAS.2008.4541469

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Yeong-Luh Ueng, Chung-Jay Yang, Zong-Cheng Wu, Chen-Eng Wu, Yu-Lun Wang:
VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. ISCAS 2008: 520-523

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