"A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range."

Hyuk-Jun Sung, Kwang Sub Yoon (1999)

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DOI: 10.1109/ISCAS.1999.780811

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Hyuk-Jun Sung, Kwang Sub Yoon:
A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. ISCAS (2) 1999: 553-556

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