"A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural ..."

Suhas Shivapakash et al. (2020)

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DOI: 10.1109/ISCAS45731.2020.9180868

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-21

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Suhas Shivapakash, Hardik Jain, Olaf Hellwich, Friedel Gerfers:
A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. ISCAS 2020: 1-5

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