"A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET."

Ping Lu et al. (2022)

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DOI: 10.1109/ISCAS48785.2022.9937248

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-17

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Ping Lu, Charlie Boecker, Bupesh Pandita, Minhan Chen, Sheethal Nayak:
A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET. ISCAS 2022: 1714-1718

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