"Architecture of a multi-slot main memory system for 3.2 Gbps operation."

Jaejun Lee et al. (2010)

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DOI: 10.1109/ISCAS.2010.5537702

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Jaejun Lee, Sungho Lee, Joontae Park, Sangwook Nam:
Architecture of a multi-slot main memory system for 3.2 Gbps operation. ISCAS 2010: 3857-3860

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