"A 1.2V multi Gb/s/pin memory interface circuits with high linearity and ..."

Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun (2005)

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DOI: 10.1109/ISCAS.2005.1464970

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun:
A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch. ISCAS (2) 2005: 1847-1850

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