"An Accurate FPGA Online Delay Monitor Supporting All Timing Paths."

Weixiong Jiang et al. (2020)

> Home

Details and statistics

DOI: 10.1109/ISCAS45731.2020.9181070

access: closed

type: Conference or Workshop Paper

metadata version: 2025-02-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/JiangLYH20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/JiangLYH20
Weixiong Jiang, Rui Li, Heng Yu, Yajun Ha:
An Accurate FPGA Online Delay Monitor Supporting All Timing Paths. ISCAS 2020: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.