"FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine."

Hanan M. Hassan, Ahmed F. Shalash, Karim Mohamed (2011)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2011.5937798

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/HassanSM11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/HassanSM11
Hanan M. Hassan, Ahmed F. Shalash, Karim Mohamed:
FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine. ISCAS 2011: 1255-1258

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.