"A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at ..."

Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi (2024)

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DOI: 10.1109/ISCAS58744.2024.10558036

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-16

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Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi:
A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS. ISCAS 2024: 1-5

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