"Verilog-a modeling of Silicon Photo-Multipliers."

Gianluca Giustolisi et al. (2016)

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DOI: 10.1109/ISCAS.2016.7527479

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-02

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Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo:
Verilog-a modeling of Silicon Photo-Multipliers. ISCAS 2016: 1270-1273

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