"Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC ..."

Bruno Esperanca et al. (2008)

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DOI: 10.1109/ISCAS.2008.4541394

access: closed

type: Conference or Workshop Paper

metadata version: 2019-02-04

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Bruno Esperanca, João Goes, Rui Santos-Tavares, Acacio Galhardo, Nuno Paulino, Manuel Medeiros Silva:
Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC. ISCAS 2008: 220-223

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