"Multi-standard low-power DDR I/O circuit design in 7nm CMOS process."

Moo Sung Chae, Tom Wilson, Eric Naviasky (2017)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2017.8050331

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/ChaeWN17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/ChaeWN17
Moo Sung Chae, Tom Wilson, Eric Naviasky:
Multi-standard low-power DDR I/O circuit design in 7nm CMOS process. ISCAS 2017: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.