"CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency ..."

Haocong Luo et al. (2020)

> Home

Details and statistics

DOI: 10.1109/ISCA45697.2020.00061

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isca/LuoSHPYOPM20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isca/LuoSHPYOPM20
Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, Abdullah Giray Yaglikçi, Lois Orosa, Jisung Park, Onur Mutlu:
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off. ISCA 2020: 666-679

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.