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"The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays."

M. S. Hrishikesh et al. (2002)

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DOI: 10.1109/ISCA.2002.1003558

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/isca/HrishikeshBKSJF02
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  - https://dblp.org/rec/conf/isca/HrishikeshBKSJF02
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. ISCA 2002: 14-24

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