"Scenario for catastrophic failure in interconnect structures under chip ..."

Masaki Omiya et al. (2015)

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DOI: 10.1109/IRPS.2015.7112751

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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  - https://dblp.org/rec/conf/irps/OmiyaKSKSNSNSN15
Masaki Omiya, Shoji Kamiya, Nobuyuki Shishido, Kozo Koiwa, Hisashi Sato, Masahiro Nishida, Takashi Suzuki, Tomoji Nakamura, Toshiaki Suzuki, Takeshi Nokuo:
Scenario for catastrophic failure in interconnect structures under chip package interaction. IRPS 2015: 5

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