"An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using ..."

Juan Andrés Pérez-Celis et al. (2016)

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DOI: 10.1109/IPDPSW.2016.174

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Juan Andrés Pérez-Celis, José Martínez-Carranza, Alicia Morales-Reyes, Claudia Feregrino Uribe, René Cumplido:
An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter. IPDPS Workshops 2016: 156-161

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